Instead of stopping with each error, the tool continues compilation after an error is found, generating a report of all the errors encountered so that they can be addressed at once, without re-compiling between each fix. It is especially useful for FPGA-based prototypers who may not be as familiar with the source HDL code. The continue-on-error feature addresses FPGA-based prototypers' need for fast turnaround time by eliminating the need to address errors one at a time as they are found during HDL compilation.
#Synplify pro power report software
The new Synplify 2012.03 software release offers FPGA designers significantly shorter design cycles. This is especially useful for high reliability applications where errors cannot be tolerated.” “The new 2012.03 Synplify Premier product infers Xilinx error correcting memory and automatically makes the connections to the design. “Designs targeted for safety critical applications such as those used in defense, aerospace, medical, industrial control and automotive markets require the highest level of quality and reliability,” said Tom Feist, Senior Director of Design Methodology Marketing at Xilinx.
#Synplify pro power report code
This capability is especially important with SoC prototypers who may not be intimately familiar with the HDL code they have to implement in an FPGA. In addition, the Synplify Premier software is enhanced with a new continue-on-error feature to address FPGA designers' need for fast turnaround time by enabling them to generate a report and fix all errors resulting from missing or incorrect design definitions at the end of the hardware description language (HDL) compilation step rather than incrementally fixing an error and rerunning the compile step. The Synplify 2012.03 products include improved synthesis algorithms that accelerate runtime by up to 30 percent.
The folks at Synopsys have announced the availability of the latest release of their Synplify Pro and Synplify Premier FPGA synthesis tools.